This invention relates to electrically erasable programmable read only memories (EEPROMs), and more specifically to flash EEPROMs. (A flash EEPROM is an EEPROM which has three distinct modes of operation: a read mode in which data is read from the EEPROM, a programming mode in which data is stored in the EEPROM, and an erase mode in which the entire contents of the EEPROM are erased.)
One type of prior art memory device is a non-flash EEPROM. When it is desired to program a non-flash EEPROM, program data is provided on the EEPROM data bus, an address is provided on the EEPROM address bus, and the EEPROM automatically executes an erase cycle in which the selected address is erased, followed by a programming cycle, in which the selected address is loaded with the program data.
Another type of memory device is the flash EEPROM which can enter an erase mode independently of whether the flash EEPROM is to be programmed, or enter the programming mode independently of whether the flash EEPROM is to be erased Typically, such a flash EEPROM includes a programming voltage pin, and when a programming voltage is asserted on the programming voltage pin, the flash EEPROM will go into either the erase or programming mode. It is necessary to communicate to the flash EEPROM whether it is desired to program or erase the flash EEPROM. This is typically done by the either (1) providing an extra pin on the flash EEPROM for providing a signal indicative or whether a programing or erase operation is desired, or (2) designing one or more of the other flash EEPROM pins so that if these pins receive a signal which is in excess of conventional TTL voltage levels, the flash EEPROM will enter the erase mode, but otherwise will enter the programming mode.
It is known in the art to provide microprocessor systems including a microprocessor coupled to various devices such as EEPROMs, static RAMs, and peripheral I/0 devices. The microprocessor provides a write control pulse to control the flow of data from the microprocessor to the devices connected thereto. Typical microprocessors are designed to communicate with devices which can store data in a very short time period. Thus, the write control pulse is generally on the order of approximately 100 nanoseconds long. However, it typically requires between several hundred microseconds and several milliseconds to store data in an EEPROM. Accordingly, in the prior art, additional integrated circuits are required to permit a microprocessor to store data in a flash EEPROM.
FIG. 1 illustrates a prior art circuit 10 including a microprocessor 14 for communicating with a flash EEPROM 12. (Typically, other devices such as static RAMs and peripheral I/0 devices are also coupled to microprocessor 14, but these other devices are not shown in FIG. 1 to simplify the illustration.) The circuit of FIG. 1 is described by Samba Murthy in an article entitled "EEPROM Programs in a Flash", published in Electronic System Design Magazine in Apr. 1987, incorporated herein by reference. When it is desired to write data to EEPROM 12, microprocessor 14 provides an address on address bus 22, data on data bus 16 and a write control pulse on a write enable lead 24. Also, during write operations, the output signal on I/0 output port lead 18 is active (low), and the output signal on I/0 output port lead 20 is inactive (high). When the signal at lead 18 is low, a logic and switching circuit 19 raises voltage VPP from 5 to 12 volts, and the write control pulse on lead 24 is communicated to EEPROM 12 via an OR gate 13.
Eleven of the address bus lines within address bus 22 are connected directly from microprocessor 14 to EEPROM 12. A set 23 of three of address bus lines 22 are coupled to EEPROM 12 via logic and switching circuit 19. When the signal at lead 20 is inactive (e.g. during reading and writing operations), circuit 19 communicates the address signals on lines 23 to EEPROM 12.
The write pulse on lead 24 controls the timing for writing data to the various devices connected to microprocessor 14, and typically lasts on the order of 100 nanoseconds. At the conclusion of the write operation, the signal at lead 24 goes inactive and microprocessor 14 then goes on to accomplish other tasks. However, storing data in EEPROMs such as EEPROM 12 typically requires a much longer write pulse, e.g. a write pulse lasting on the order of 100 microseconds. Accordingly, circuit 10 includes a circuit 26 which provides a wait signal on a lead 28 for a predetermined time period (e.g. 100 microseconds), which causes microprocessor 14 to go into a wait state and leave the write enable signal on lead 24 in an active (low) state for the duration of the wait signal, thereby permitting EEPROM 12 to store the data provided on data bus 16. Thereafter, the wait signal on lead 28 goes inactive and microprocessor 14 resumes normal operation. Unfortunately, circuits such as circuit 26 represent an additional integrated circuit in circuit 10 and are therefore expensive and undesirable. In addition, by causing microprocessor 14 to enter the wait state, microprocessor 14 is unable to perform other tasks while waiting for EEPROM 12 to store data.
It is also necessary to be able to cause flash EEPROM 12 to go into an erase mode to erase the data stored therein in response to signals from microprocessor 14. When it is desired to erase EEPROM 12, the signal at I/0 output port leads 18 and 20 go active (low), thereby causing circuit 19 to raise the voltage at VPP pin 30 and at address pins 21 of EEPROM 12 to about 12 volts. The presence of 12 volts at pins 21 is sensed by EEPROM 12, which responds by erasing the data stored therein. Unfortunately, circuit 19 represents several additional integrated circuits within circuit 10, thereby adding to the expense of circuit 10. In addition, the circuit 19 must be able to withstand high voltages, e.g. about 12 volts. Circuits of this nature tend to be slow, thereby impeding the speed of communication of addresses to EEPROM 12 and thus slowing circuit 10 during reading and writing operations.
Another method of causing EEPROM 12 to enter the erase mode would be to add an extra pin to EEPROM 12 for receiving an erase command signal from microprocessor 14. However, providing extra pins in an EEPROM is expensive and undesirable.